1. Field of the Invention
This invention relates to a MOS structure type semiconductor memory device and, more particularly, relates to a non-volatile semiconductor memory device having a charge storage layer (e.g., a floating gate) and a control gate.
2. Description of the Related Art
Electrically rewritable non-volatile memory devices realized by using a MOSFET structure memory comprising floating gates are normally referred to as EEPROMs in the technology of non-volatile memories. The memory array of an EEPROM of this type is typically formed by arranging a memory cell at each of the intersections of the row and column lines of the device. More specifically, the two adjacent memory cells are made to share a common drain which is held in contact with a corresponding column line so that the contact section takes a minimum area of the cells. With such an arrangement, however, a contact section is required for each drain that is common to a pair of memory cells and takes a considerable portion of the area occupied by the cells.
In an attempt to further reduce the area of a contact section, there has been proposed an EEPROM in which memory cells are serially connected to make NAND cells. The NAND cells can be collectively erased by causing them to simultaneously emit electrons through their floating gates and, thereafter, electrons may be injected only into the floating gates of selected memory cells to write data there. For collectively erasing the memory cells, their control gates are held to level "L" while the wells are held to level "H". For select data programming, data is sequentially programmed into the cells closer to the source and then into the cells closer to the drain. During this operation, the voltage of the drain of the selected cell is raised from level "L" to an intermediary level and that of the control gate of the selected cell is raised to level "H" so that electrons may be injected into the floating gate from the substrate.
The voltage of the control gate has to be substantially equal to that of the drain for all the unselected memory cells located closer to the drain than the selected memory cell in order to deliver the potential of the drain to the selected cell. This is because of the voltage applied to the drain, only the portion equal to the voltage applied to the control gate less the threshold voltage of the memory cell can be delivered to the source.
With any known NAND cells, however, the threshold voltage of each cell is unequivocally defined by the voltage of the floating gate because the latter is arranged to cross the channel region. Therefore, the data stored in a selected cell cannot be read out if the threshold voltage is higher than the voltage (Vcc) applied to the control gate of an unselected cell.
FIG. 1 of the accompanying drawings schematically shows the distribution of threshold voltages of the memory cells of a memory device of the type under consideration. For reading out data, a voltage of Vcc (=4.5 to 5.5V) is applied to the control gate of each unselected memory cell and the memory cells of both the programming and erasing sides are turned ON. Then, the selected memory cell would not become ON and no data would be read out of it if the threshold voltage of the programming side memory cell is higher than Vcc (e.g., 6V).
Thus, if the threshold voltage of a memory cell is determined as a function of the voltage of the floating gate, a wide dispersion may become observable in the threshold voltage at the time of data programming. This would some memory cells show a high threshold voltage and the selected memory cell would not become ON with the control gate voltage of the unselected memory cell;
A NAND cell proposed to by pass the above described problem is shown in FIGS. 2 through 4B, of which FIG. 2 is a plan view and FIG. 3 a circuit diagram of an equivalent circuit of the cell while FIGS. 4A and 4B are cross sectional views taken along lines 4A--4A and 4B--4B of FIG. 2.
A diffusion layer 7 for producing sources and drains is formed on a substrate region 1 (or p-type well region) of a substrate separated from the remaining regions by an element separating region 2. Then, floating gates 4 (4.sub.1 to 4.sub.4) are formed with a first insulation film 32 disposed therebetween and thereafter control gates 6 (6.sub.1 to 6.sub.4) are formed with second and third gate insulation films 31 and 33 arranged therebetween for each memory cell unit. A bit line 9 is formed on the control gates 6 via an interlayer insulative layer 8. In a NAND cell having the above described configuration, the floating gates 4 occupy only part of the channel region. In other words, the former does not completely cross and partly covers the latter along the transversal direction of the latter and transistors (T1 to T4) are formed in the uncovered area as shown in FIGS. 2 and 3 so that the threshold voltage in the position direction of the memory cell is determined by the part of the channel region that is not covered by the floating gates 4.
With a memory cell of the above described arrangement, however, the performance of the device can vary significantly if the element region and the corresponding floating gate are not correctly aligned. If such misalignment takes place between the element region and the floating gate, there may be produced an area x where the floating gate 4 overlies the gate insulation film 32 as shown in FIGS. 2 and 4A. Then, the performance of the memory cell particularly in terms of coupling ratio can vary as a function of the value of x to give rise to significant variances in the programming and reading voltages. Additionally, the performance of the transistors (T1-T4 of FIGS. 2 and 3) in the areas that are not covered by the respective floating gates can also vary to make the overall performance of the memory cell very unstable.
The influence of the misalignment can affect much more remarkably the overall performance of the memory cell if the channel width is reduced to achieve an enhanced degree of integration. Thus, the problem of misalignment becomes unsurmountable in proportion to the effort for a higher degree of integration and downsizing.
A memory cell which forms the overlap area x of the floating gate 4 an the gate insulative film 32 in the channel area and has no floating gate 4 on the element separating film 2 is proposed (FIG. 4C). In this memory cell, even if the misalignment of area x and the element separating area occurs, it is necessary to enlarge the size y of FIG. 4C to avoid overlapping areas thereof. Therefore, it is difficult to perform higher integration and downsizing.
As described above, with a NAND-type memory cell in which the floating gate partly covers the channel region, the problem of varying performance of the device as a function of misalignment of the floating gate and the element region provides a major obstacle to be cleared in the effort of downsizing.